Integrated semiconductor receiver or buffer circuits having low voltage input levels or swings, such as outputs from bipolar circuits, are known in the prior art.
U.S. Pat. No. 4,438,352, filed on Aug. 17, 1982, by M. M. Mardkha discloses a transistor-transistor logic (TTL) compatible CMOS input buffer which includes an input terminal connected to gate electrodes of a series circuit having first and second P channel transistors and a first N channel transistor and a second N channel transistor connected in parallel with the second P channel transistor, the output terminal being the common point between the first N channel transistor and the second P channel transistor.
Other examples of TTL to CMOS input buffers or level shift circuits include U.S. Pat. No. 4,258,272, filed on Mar. 19, 1979, by J. Y. Huang, U.S. Pat. No. 4,295,065, filed on Aug. 13, 1979, by P. K. Hsieh et al and U.S. Pat. No. 4,475,050, filed on May 5, 1983 by G. F. Noufer.
Also, U.S. Pat. No. 4,031,409, filed on May 26, 1976, by S. Shimada et al discloses a circuit for converting a binary signal from a bipolar transistor logic circuit to the levels required for binary signals by insulated gate field effect transistor circuits.
An emitter coupled logic (ECL) compatible CMOS circuit is disclosed in U.S. Pat. No. 4,437,171, filed Jan. 7, 1982, by E. L. Hudson et al.
Interfacing CMOS circuits to bipolar technologies poses some difficulties because the bipolar signal level changes or swings are much smaller than that which is required for the operation of the normal CMOS circuit. A CMOS circuit having a normal 5 volt power supply is generally optimized to switch its transistor elements at approximated 2.5 volts. However, known circuits in the bipolar technology have, e.g., the least positive up level of 1.5 volts and the least negative down level of 0.6 volts. Other bipolar circuits, e.g., the TTL circuits, have corresponding levels of 2 volts and 0.8 volts. It can be seen that the output voltages from these bipolar circuits cannot be readily used to switch the normal CMOS circuits. By modifying the dimensions of the N channel and P channel devices of the CMOS circuits, the center of the switching point can be shifted, however, the variations due to power supply and process parameters remain intolerably large.